`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2025/01/25 16:03:02
// Design Name: 
// Module Name: key1_decode
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module key2_mode 
    #(
        parameter  KEY2_MODE7_MAX = 4'd3
    )
    (
    input                   clk,
    input                   rst,
    input                   key2_pulse,
	input   [3:0]        	oled_mode,
    output reg [3:0]        key2_mode7
    );
    
    always @(posedge clk  or  negedge rst)begin
         if (!rst) 
            key2_mode7 <= 4'd0;
         else if (key2_pulse && oled_mode == 7)
            if(key2_mode7 == KEY2_MODE7_MAX - 1'b1)
                key2_mode7 <= 1'b0;
            else
                key2_mode7 <= key2_mode7 + 1'b1;
         else
            key2_mode7 <= key2_mode7;
   end        
    
endmodule
